In the field of large, very high performance computers, usually referred to as supercomputers, a vector processing architecture is usually provided in order to achieve very high data processing rates in computations involving ordered sets of data, or vectors. A very successful supercomputer vector processing architecture is disclosed in U.S. Pat. No. 4,128,880 by Seymour R. Cray and assigned to Cray Research, Inc. In that architecture, a plurality of vector registers are provided to hold vectors for sending as operands to functional units, and for receiving and holding result vectors from functional units. For maximum speed, fully segmented functional units are provided wherein all information arriving at the functional unit or moving within the functional unit is captured and held at the end of every time period. Vector registers used as operand registers for a given vector process transmit individual elements to a functional unit at the rate of one element per time period. Once the startup time, or functional unit time, has passed, the functional unit provides successive result elements on successive time periods, and these are transmitted as elements of a result vector to a vector register acting as the result register for that particular vector process. Vector transfers between vector registers and main memory may also be accomplished at one element per time period.
By providing a number of functional units (for example, floating point multiply, integer add, logical operations, etc.) and a number of vector registers (for example, eight), any of which may be associated by program instruction control with any functional unit or memory, computers according to U.S. Pat. No. 4,128,880 may have numerous vector processes proceeding simultaneously, thereby achieving extremely high data processing rates.